1. Field of the Invention
The present invention relates to a semiconductor device used, e.g., for switching high currents.
2. Background Art
Japanese Laid-Open Patent Publication No. H08-078534 discloses a semiconductor device having a MOS structure. This semiconductor device has low impurity density polysilicon provided on its substrate with a gate insulating layer interposed therebetween. A metal silicide is provided on the polysilicon. That is, the semiconductor device has a gate electrode made up of the polysilicon and the metal silicide. The reason for the use of such low impurity density polysilicon is so that, when a gate voltage is applied to the gate, a depletion layer forms and extends in the polysilicon so as to reduce the voltage applied to the substrate.
Further, IEEE Electron Device letters EDL-10 (5) p192 (1989) “Anomalous CV characteristics of implanted poly MOS structure in n+/p+ dual-gate CMOS technology” discloses the fact that a depletion layer forms in gate electrodes.
When a semiconductor device is turned on by applying a voltage to its gate, the resulting saturation current of the semiconductor device must be between a predetermined allowable maximum saturation current and a predetermined allowable minimum saturation current. It should be noted that the gate voltage is bound to vary within a certain range. Therefore, the semiconductor device must be designed such that its saturation current is always between the allowable maximum saturation current and the allowable minimum saturation current even if the gate voltage varies over that range. That is, it is desirable to reduce the rate of change of the saturation current with respect to changes in the gate voltage.
In the case of the semiconductor device disclosed in the above Japanese Laid-Open Patent Publication, the rate of change of its saturation current with respect to its gate voltage is low, since a portion of the gate voltage is dropped across the polysilicon. This semiconductor device, however, is disadvantageous in that a thick (or long) depletion layer is always formed in the polysilicon when a voltage is applied to the gate, making it difficult to apply an adequate voltage to the gate insulating layer. To avoid this problem, for example the impurity density of the channel layer, in which an inversion layer is formed, may be reduced to reduce the threshold voltage. This, however, may result in latch-up.